1. Field of the Invention
The present invention relates to Complementary Metal Oxide Semiconductor (CMOS) integrated circuits and more particularly to the semiconductor device structures that are placed at the input of the integrated circuits to protect said integrated circuits from damage as a result of excess voltage due to an electrostatic discharge (ESD) event.
2. Description of Related Art
Referring to FIG. 1, an internal integrated circuit is connected to a PAD on a semiconductor substrate to pass signals into and out of said internal Integrated circuit. N-type Metal Oxide Semiconductor (NMOS) transistor N1 and P-type Metal Oxide Semiconductor (PMOS) transistor P1 are connected between the PAD and the voltage reference source Vss and the voltage power supply Vcc, respectively. The NMOS transistor N1 and the PMOS transistor P1 are each configured as reversed biased MOS diodes.
A model ESD source such as the ESD generator consists of resistor R1, capacitor C1, and switch S1. When switch S1 is such that the resistor R1 and capacitor C1 are connected to the ESD voltage source V1, the capacitor C1 is charged to the ESD voltage V1. The magnitude of the ESD Voltage V1 is on the order of many hundreds of volts, even thousands of volts.
As the switch S1 changes the connection from the ESD voltage source V1 to the resistor R1, the ESD voltage V1, that is present on the capacitor C1, is transferred to the PAD through the resistor R1. When the voltage present on the PAD exceeds the breakdown voltage of the drain to substrate junction of the NMOS transistor N1 and the VSS is connected to the ground reference voltage and the point normally connected to the voltage power supply Vcc is disconnected and is floating, the NMOS transistor N1 begins to conduct and the voltage of the resistor R2 is clamped at the level of the breakdown voltage of the NMOS transistor N1 preventing damage to the internal integrated circuit. If the polarity of the ESD voltage source V1 is reversed and the node VSS that is normally connected to the ground reference voltage and the node that is normally connected to the voltage power supply Vcc is now connected to the ground reference voltage, the PMOS transistor P1 is in breakdown to clamp the voltage level at the resistor R2 to a level of the breakdown voltage of the PMOS transistor P1 less the value of the Vcc, to prevent damage again to the internal integrated circuits.
FIG. 2a illustrated the cross sectional view of a standard lightly doped drain (LDD) NMOS transistor and FIG. 2b illustrates the cross sectional view of a LDD PMOS transistor. The LDD NMOS and PMOS transistors form the standard devices that comprise the internal integrated circuits of FIG. 1. In FIG. 2a, N.sup.+ diffusions 10 and 40 respectively form the drain and source on a P-type substrate 60. The P-type substrate 60 has a P.sup.+ diffusion 50 formed in it to provide a high conductivity path for the connection with the ground reference terminal 55. The N.sup.- regions 20 and 30 form the lightly doped drains, which when the NMOS transistor is conducting help decrease the length of the gate channel 70 to improve performance of the NMOS transistor.
An insulating film 80 is deposited above the gate channel 70 to form the gate oxide and the metal region 90 forms the gate of the NMOS transistor.
To create the input protection device N1 of FIG. 1, the gate 90 and the source 40 are connected to the ground reference terminal 55, while the drain is connected to the PAD 5.
In FIG. 2b, P.sup.+ diffusions 110 and 140 respectively form the drain and source in an N-well 165 on a P-type substrate 160. The N-well 165 has a N.sup.+ diffusion 150 formed in it to provide a high conductivity path for the connection with the voltage supply terminal (Vcc) 155. The P.sup.- regions 120 and 130 form the lightly doped drains, which when the PMOS transistor is conducting help decrease the length of the gate channel 170 to improve performance of the PMOS transistor.
An insulating film 180 is deposited above the gate channel 170 to form the gate oxide and the metal region 190 forms the gate of the NMOS transistor.
To create the input protection device P1 of FIG. 1, the gate 190 and the source 140 are connected to the ground reference terminal 155, while the drain is connected to the PAD 105.
FIG. 3a illustrates the mechanism of an ESD event on an NMOS transistor as shown in FIG. 2a. The drain 410 and the source 440 are diffusions of N.sup.+ material into P-type substrate 460. The LDD regions are formed by the N.sup.- diffusions 420 and 430. The insulating film 480 forms the gate oxide, while the metal layer 490 forms the gate for the NMOS transistor. The P-type substrate 460 has a P.sup.+ diffusion 450 to provide a region of high conductivity that will connect the P-type substrate 460 to the ground reference terminal 455. The gate 490 and the source 440 are connected to the ground reference terminal 455 and the drain 410 is connected to the PAD 405, to form the connections for the NMOS transistor N1 of FIG. 1.
The NMOS transistor has parallel parasitic bipolar transistors 425 and 426 that are formed by the semiconductor structure of the NMOS transistor. The emitters of the parasitic transistor 425 and 426 are the source diffusions 430 and 440. The collectors are the drain diffusion 410 and 420, while the bases are formed by the area of the P-type substrate 460 between the source 430 and the drain 410 of the NMOS transistor. The base resistor 465 is the resistance of the P-type substrate 460 to the P.sup.+ diffusion 450.
The ESD generator 401 operates by switch S1 connecting the capacitor C1 with the voltage source V1. As with the ESD generator of FIG. 1, the amplitude of the voltage source V1 may be many hundreds of volts and in fact may be on the order of 1000 V-2000 V. The capacitor is charged to this voltage. The switch is changed to contact the resistor 405. The voltage is transferred throught the resistor 405 to the drain diffusions 4410 and 420. A large voltage field 415 builds in the gate oxide 480 between the gate 490 and the drain diffusions 410 and 420. This large field stimulates a Fowler-Norheim Tunneling current and the band to band current 412 from the gate 490 to the drain diffusions 410 and 420. Also, the large voltage at the drain diffusions 410 and 420 cause a voltage field Eh 417 between the drain diffusions 410 and 420 and the P-type substrate 460. This flow of electrons to the depletion region 411 at the drain diffusions 410 and 420 causes a flow of hole current 416 and 418 to the P-type substrate 460. The current 418 develops a voltage across the base resistor 465 which is sufficient to place the parasitic transistor 425 into conduction, thus driving the NMOS transistor as shown in FIG. 2a into the snap-back to the clamp the voltage to a level that will prevent damage to gate oxide 480 and the internal integrated circuit of FIG. 1.
FIG. 3b is an energy band diagram of the process of FIG. 3a. The electrons 530 from the gate are forced across the gate oxide 550 by the field from the drain diffusions 410 and 420 of FIG. 3a. At the same time the electrons 520 are forced into the depletion region 560 by the electric field Eh 417 of FIG. 3a. This causes the counter hole flow 510 that is the hole current 418 of FIG. 3a.
FIG. 3c is a graph of the voltage 600 developed from the drain diffusions 410 and 420 and the ground 455 of FIG. 3a and the current 650 is the current flow through the parasitic resistor 425 of FIG. 3a. At the beginning of an ESD event having large current, the current path expands from the lightly doped region 420 to the N.sup.+ region 410 of FIG. 3a. The snap-back voltage 610 is determined by the N.sup.+ doping concentration. The snap-back voltage (Vsp) is: EQU Vsp=IRd+Vd+0.7
where: ##EQU1## I is the current through drain 410 and 420 of FIG. 3a Rd is the series resistance of the N.sup.+ 410 and the n.sup.- 420 of FIG. 3a.
.epsilon.E.sup.2 max is the maximum voltage field between the drain N.sup.+ 410 and the n.sup.- 420 to the substrate 460. PA1 q is the charge of the electron. PA1 Nd is the doping concentration of the drain N.sup.+ 410. PA1 n is the electron density.
As the current decreases, the current path shrinks to the lightly doped region 420 of FIG. 3a. The snap-back voltage is determined by the n.sup.- doping concentration of the lightly doped drain section 420. From the above equation the it can be seen that the snap voltage is proportional to ##EQU2## such that the level 630&gt;the level 610. The level 630 is sufficiently high as to cause damage to the gate oxide 480 of FIG. 3a and the internal integrated circuits of FIG. 1.
FIGS. 2c and 2d are cross sectional view of an abrupt junction NMOS transistor and a PMOS transistor. These two transistors are fabricated according to U.S. Pat. No. 5,246,872 (Mortensen) using the same processing as the LDD devices of FIGS. 2a and 2b.
The N.sup.+ diffusions 210 and 240 respectively form the drain and source on the P-type substrate 260. The P.sup.+ diffusion 250 provides a low resistivitiy path to connect the P-type substrate 260 to the ground reference terminal 255. The insulating film 280 forms the gate oxide with the metal film 290 forming the gate. The channel 270 is region beneath the gate oxide 280 between the drain 210 and the source 240.
In the N-well diffusion 365 on the P-type substrate 360, the PMOS transistor is formed by the P.sup.+ diffusion 310 and 340, which are the source and the drain respectively, the gate oxide 380 and the gate 390. The N-well is connected to the Vcc 355 through the N.sup.+ diffusion 350.
To form the connections for the NMOS transistor N1 of FIG. 1, the drain 210 is connected to the PAD 205 and the source 240 and gate 290 are connected to the ground reference terminal 255. To form the connections of the PMOS transistor P1 of FIG. 1, the drain 310 is connected to the PAD 305 and the source 340 and gate 390 are connected to the Vcc 355.
With an abrupt junction as shown in FIG. 2c, the voltage field in the gate oxide is not as great and the band to band tunneling will be sufficient to cause the parasitic transistor to conduct. FIG. 3d is a graph of the voltage 900 from the drain 210 of the NMOS transistor and the ground reference terminal 255 of FIG. 2c and of the current 950 through the parasitic transistor formed by the drain 210, the source 240, and the area beneath the source and drain 270 of FIG. 2c. When an ESD voltage is applied to the PAD 205 of FIG. 2c, the voltage 900 and the current 950 rise to the high level 905 until the parasitic transistor conducts. The voltage 900 is clamped to level 910, while the current 950 decays as the charge from the ESD generator is removed to the ground reference terminal 255 of FIG. 2c. The voltage level 910 is sufficiently low as to prevent damage to the gate oxide 280 of FIG. 2c and the internal integrated circuits of FIG. 1.
For the same drawn channel length, the duration of the peak 905 is somewhat because of the length of the channel 270 of FIG. 2c, since this is the base width of the parasitic transistor. This additional time is sufficient to cause stress in the gate oxide of internal integrated circuitry of FIG. 1.
U.S. Pat. No. 5,142,345 (Miyata) discloses a semiconductor device structure that can form a memory device, an LDD structure, and ESD input protection device on the same semiconductor substrate using the same manufacturing method.